A circuit consists of two synchronously clocked J-K flip-flops connected as follows :

J0 = K0 = Q̅1, J1 = Q1, K1 = Q̅ 0. The circuit acts as a

This question was previously asked in
ESE Electronics 2014 Paper 2: Official Paper
View all UPSC IES Papers >
  1. Counter of mod 2
  2. Counter of mod 3
  3. Shift-right register
  4. Shift-left register

Answer (Detailed Solution Below)

Option 1 : Counter of mod 2
Free
ST 1: UPSC ESE (IES) Civil - Building Materials
6.2 K Users
20 Questions 40 Marks 24 Mins

Detailed Solution

Download Solution PDF

Circuit diagram:

F2 Shubham 16.11.20 Pallavi D 3

State Table:

CLOCK

J1

K1

J0

K0

 

 

 

Q0

0

1

1

Initially 0

0

1st Cock

0

1

1

1

0

1

2nd Clock

1

0

1

1

1

0

3rd Clock

0

1

0

0

0

0

 

Since it switches between two states only, the counter is a MOD 2 counter.
Latest UPSC IES Updates

Last updated on May 28, 2025

->  UPSC ESE admit card 2025 for the prelims exam has been released. 

-> The UPSC IES Prelims 2025 will be held on 8th June 2025.

-> The selection process includes a Prelims and a Mains Examination, followed by a Personality Test/Interview.

-> Candidates should attempt the UPSC IES mock tests to increase their efficiency. The UPSC IES previous year papers can be downloaded here.

More Asynchronous Counters Questions

Get Free Access Now
Hot Links: teen patti gold real cash teen patti master list teen patti cash all teen patti master teen patti master app