Testbook Logo
Exams SuperCoaching Test Series Skill Academy
More
English
Hindi

Question

Download Solution PDF

In a JK flipflop, J and K inputs are set to logic 1, the output Q(0) will be _______ when Q(-1) is _________.

This question was previously asked in
HPCL Engineer Instrumentation 11 Aug 2021 Official Paper
Download PDF Attempt Online
View all HPCL Engineer Papers >
  1. 0, 0
  2. 1, 1
  3. undefined, 1
  4. 1, 0

Answer (Detailed Solution Below)

Option 4 : 1, 0
Free Tests
View all Free tests >
Free
Environmental Engineering for All AE/JE Civil Exams Mock Test
10.6 K Users
20 Questions 20 Marks 20 Mins
Start Now

Detailed Solution

Download Solution PDF

The truth table of a J-K Flipflop is as shown:

J

K

Qn+1

0

0

Qn

0

1

0

1

0

1

1

1

Q̅n

 

Observations:

  • When J = 0, K = 0, and using the clock,  the output will be 1.
  • When J = 1, K = 0, and using the clock, the output will be 1.
  • When a synchronous pre-set input is used the output will be 1.
  • J = 1, K = 1, the output will toggle. If the previous output is 1, then the next output will be 0 and vice-versa. 
Download Solution PDF
Latest HPCL Engineer Updates

Last updated on Jun 2, 2025

-> HPCL Engineer 2025 notification has been released on June 1, 2025.

-> A total of 175 vacancies have been announced for the HPCL Engineer post in Civil, Electrical, Mechanical, Chemical engineering.

-> HPCL Engineer Online application will be activated from 1st June 2025 to 30th June 2025.

-> Candidates with a full-time engineering discipline in the relevant stream are eligible to apply.

-> The selection will be based on a Computer Based Test Group Task and/or Interview. Prepare for the exam using HPCL Engineer Previous Year Papers.

More Flip-Flop Questions

Q1.A flip-flop can store:
Q2.A single flip-flop is a modulo __________ counter.
Q3.The basic building block of sequential logic circuit is-
Q4.What is the characteristic of a master-slave flip-flop?
Q5.Direction: The item consists of two statements, one labelled as 'Statement (I)' and the other as 'Statement (II)'. You are to examine these two statements carefully and select the answers to these items using the code given below. Statement (I): The set-up time and hold time are met, the data at the D input is copied to the Q output after a worst-case propagation delay denoted by tc-q. Statement (II): The set-up time is the time the data input must be valid before the clock transition and the hold time is the time the data input must remain valid after the clock edge. Critical path is the longest data path.
Q6.The arrangement of a minimum number of N flip-flops can be used to construct any counter with a modulus given by the equation
Q7.How many flip-flops are required to build a binary counter that counts from 0 to 4095? 
Q8.A BCD counter can be constructed using: 
Q9.How is a J-K flip-flop made to toggle?

More Sequential Circuits Questions

Q1.How many distinct states are there are in an n-bit ring counter?
Q2.No. of Flip flop required for designing synchronous counter having 5 states with counting sequence : 0 = > 1 = > 6 = > 10 = > 4 will be :
Q3.A flip-flop can store:
Q4.A single flip-flop is a modulo __________ counter.
Q5.The basic building block of sequential logic circuit is-
Q6.What is the characteristic of a master-slave flip-flop?
Q7.Direction: The item consists of two statements, one labelled as 'Statement (I)' and the other as 'Statement (II)'. You are to examine these two statements carefully and select the answers to these items using the code given below. Statement (I): The set-up time and hold time are met, the data at the D input is copied to the Q output after a worst-case propagation delay denoted by tc-q. Statement (II): The set-up time is the time the data input must be valid before the clock transition and the hold time is the time the data input must remain valid after the clock edge. Critical path is the longest data path.
Q8.The arrangement of a minimum number of N flip-flops can be used to construct any counter with a modulus given by the equation
Q9.How many flip-flops are required to build a binary counter that counts from 0 to 4095? 
Suggested Test Series
View All >
Vocabulary Master for All Government Exams Mock Test
309 Total Tests with 1 Free Tests
Start Free Test
HPCL Engineer Mock Test 2025
80 Total Tests with   3 Free Tests
Start Free Test

More Digital Logic Questions

Q1.In a 3-to-8 decoder, how many outputs are active for any given input?
Q2.What is the 2's complement of the binary number 101110?
Q3.What is the difference between edge-triggering and level-triggering?
Q4.How many select lines are required for a 1-to-8 Demultiplexer?
Q5.If the input I = 1 and the select lines are S1 = 1, and S0 = 0, what will be the values of the four outputs in a 1-to-4 Demultiplexer?
Q6.Which of the following is a characteristic of serial binary adders?
Q7.How many distinct states are there are in an n-bit ring counter?
Q8.What is the result of applying the complement law A + A' in Boolean algebra?
Q9.Which of the following is the correct octal representation of the hexadecimal number 1A3?
Q10.Which Boolean expression correctly represents the Difference (D) output of a Full Subtractor?
Important Exams
Super Coaching
Exams
Test Series
Previous Year Papers
Objective Questions
Testbook Edu Solutions Pvt. Ltd.
1st & 2nd Floor, Zion Building,
Plot No. 273, Sector 10, Kharghar,
Navi Mumbai - 410210
[email protected]
Toll Free:1800 833 0800
Office Hours: 10 AM to 7 PM (all 7 days)
Company
About usCareers We are hiringTeach Online on TestbookPartnersMediaSitemap
Products
Test SeriesTestbook PassOnline CoursesOnline VideosPracticeBlogRefer & EarnBooks
Our Apps
Follow us on
Copyright © 2014-2022 Testbook Edu Solutions Pvt. Ltd.: All rights reserved
User PolicyTermsPrivacy
Get Free Access Now
Hot Links： teen patti rummy 51 bonus teen patti dhani teen patti app teen patti jodi