Match List-I with List-II and select the correct answer using the code given below the lists:

List - I	List - II
A. TTL	1. Low power consumption
B. ECL	2. High speed
C. CMOS	3. Low propagation delay

 

A comparison of the given logic families is as shown: 

Propagation Delay: The time taken by a ‘gate’ in propagating an input signal to the output of the gate is called ‘propagation delay’. It is measured in Nanoseconds (10-9sec.).

Fan-out: The number of units that can be connected to the output of a logic gate is called its ‘Fan-out’.

Noise Margin: In a digital circuit, the Noise Margin is the amount by which the signal exceeds the threshold for a proper ‘0’ or ‘1’.

This is schematically explained with the help of the following diagram:

• CMOS has the largest Noise Margin and ECL is having a Poor Noise Margin.
• TTL outputs are typically restricted to narrower limits, between 0 V and 0.4 V for a “LOW” and between 2.4 V and Vcc for a “HIGH”, providing at least 0.4 V of noise immunity.
• Noise Margins for CMOS chips are usually much greater than those of TTL because the VOH(min) is closer to the power supply Voltage and VOL(max) is closer to 0.