The circuit shown in the figure is:

Concept:

MOS logic circuit consists of two network transistors, a pull-down network (PDN) and a Pull-up Network (PUN) as shown:

The PDN and PUN are connected in parallel to form OR logic function and they are connected in series to form AND logic as shown:

Application:

Since we have the two MOS transistors connected in series, the resultant output will be the AND operation, with inverted output, i.e.

\(\overline Y= {AB}\)

\(Y=\overline {AB}\)